1. Field of the Invention
The present invention relates generally to a system for testing and controlling computer system logic boards that contain integrated circuits that conform to conventional test access port and boundary-scan architecture standards. More specifically, the present invention relates to a system that incorporates a bus to facilitate the sharing of test access port signals, while conserving system control signal pins on the system controller card.
2. Related Art
Due to the increased complexity in evolving surface-mount interconnection technology, testing systems have also evolved to overcome the cost and limited capability of traditional testing apparatus such as the bed-of-nails fixture. The main goals of a testing system are the abilities to confirm the correct interconnection of components, the proper function of each component and the proper interaction of components in a product. To this end, the international Joint Test Action Group (JTAG) created the IEEE 1149.1 (1990) test access port and boundary-scan architecture standard, which is incorporated herein in its entirety by reference.
One implementation of this standard involves the incorporation of a test access port (TAP) that can provide access to the test support functions built into a component or a digital logic board. The TAP is composed, as minimum, of three input connections and one output connection as defined by the IEEE 1149.1 standard. The three input connections are defined as test clock input, test data input, and test mode select input, while the output connection is defined as test data output. In addition, an optional fourth input connection defined as test reset input (TRST*) is permitted by the standard for initialization of the TAP controller.
The test clock input connection (TCK) provides the clock for the test logic, so that the test data path between components can be utilized independently of component specific system clocks. In addition, the IEEE standard requires that all stored state devices retain their state when the TCK signal is held at 0. This requirement is provided so that when a test system pauses to fetch test data from memory, the test logic may resume its operation after the TCK signal is restarted.
The test data input connection (TDI) and test data output connection (TDO) provide the test data and instruction to and from the test logic respectively, while the test mode select input (TMS) provides the control of test operations.
In addition, to ensure that test patterns can be applied, a framework is needed that can be utilized to transfer test data to or from the boundaries of individual components so that they can be tested as if they were freestanding. IEEE 1149.1 compliant components incorporating the boundary-scan technique coupled with a TAP provide such a framework. The technique involves the incorporation of a shift-register stage adjacent to each pin of a component so that signals at the component boundaries can be controlled and monitored using conventional scan testing techniques. Detailed discussion of the boundary-scan technique can be found in the IEEE 1149.1 standard (1991)).
The IEEE 1149.1 standard was originally designed as a manufacturing test facility for the testing of a single circuit card. Hence, it was adopted into stand-alone card testers that were used in manufacturing sites. However, the nature of the TAP interface standard also lends itself to be used in system control environments as well. The ability to incorporate off-the-shelf IEEE compliant testing components into a system control environment for the purpose of initialization, configuration, testing, fault isolation and recovery in the field, is a very desirable goal for computer system designers.
However, the incorporation of the IEEE TAP interface into a system control environment poses special problems. One goal in such environments is to have one system controller card managing a number of system logic boards. Complying to the IEEE 1149.1 standard will require five signals per system logic board if the optional TRST* signal is also incorporated. In a typical system environment of one system controller card and 40 target system logic boards, this requirement translates to 200 pins on the system controller card for TAP signals alone. When other control signals are then incorporated onto the system controller card, it is burdened with a tremendous number of backplane pins. The rise in backplane pins also increases cost and complexity in fault isolation during system maintenance operations.